The present invention relates to a novel arrangement of an FET, serving as access device, and a capacitor, both together forming a storage cell of a memory, e.g. a Dynamic Random Access Memory (DRAM).
In order to be able to make memory chips, logic devices and other kind of devices of high integration density, one has to find a way to further scale down certain components thereof.
Vertical field effect transistors (FETs) play an important role in different such devices. They are of particular importance in DRAMs. Another important building block of memory devices are the capacitors which actually store the information. The FETs usually serve as access devices for these capacitors. By application of appropriate signals to the word lines and bit lines of a storage cell, the respective FET can be switched to allow the charging of the corresponding capacitor.
In order to achieve a high packing density necessary for Gbit DRAM memory, it is crucial that a minimum memory cell size be maintained. This minimum cell size typically is on the order of 4F2, where F is the minimum lithographic line-width.
It is an object of the present invention to provide a way for the high density integration of access devices and capacitors, e.g. for use in a memory device.
It is another object of the present invention to provide an improved FET/capacitor arrangement which is suited for high density integration.
The present invention concerns a novel arrangement of a vertical transistor and a capacitor (e.g. a stack capacitor), and a method for operation of such an arrangement. This arrangement is well suited as memory cell of a memory device, for example.
The novel arrangement comprises an FET with a vertically arranged channel and a capacitor being formed on top of the FET""s uppermost electrode, e.g. the drain. The capacitor is interconnected with this uppermost electrode. The source electrode of the FET is coupled to a common source voltage VDD, for example. The gate electrode is linked to a word line and the capacitor""s upper electrode is connected to the bit line.
In a preferred implementation, the gate electrodes (comprising polysilicon, for example) directly connect all devices along a common word line or row line.
This new arrangement requires a novel operation scheme for the storing and reading of information, as will be described in the detailed description.
In an alternative embodiment of the present invention the doped region serving as drain and the doped region serving as source are interchanged. Such a structure can be referred to as common drain transistor capacitor stack.
The integration of a vertical FET serving as access transistor with a storage capacitor stacked on top of it allows to realize very small memory cells.
It is an advantage that the inventive cells can be made using processing steps which are compatible with current semiconductor manufacturing processes.